The present invention relates to mounting and connection devices and techniques for use with microelectronic elements such as semiconductor chips.
Complex microelectronic devices such as semiconductor chips require numerous connections to other electronic components. Typically, the microelectronic devices are mounted on substrates or external circuit elements, such as printed circuit boards, having electrical contacts, and the contacts on the chip are electrically connected to the contacts of the external circuit element. The external circuit element may have pins or other connectors adapted to accommodate other components, including additional semiconductor chips. Also, the external circuit element may have pins or other connectors adapted to connect the contacts or internal circuitry of the external circuit element to a larger assembly, thereby connecting the chip to the larger assembly.
Connections between microelectronic elements and substrates must meet several demanding and often conflicting requirements. They must provide reliable, low-impedance electrical interconnections. They must also withstand stresses caused by thermal effects during manufacturing processes such as soldering. Other thermal effects occur during operation of the device. As the system operates, it evolves heat and the components of the system, including the chip and the substrate expand. When operation ceases, the components cool and contract. When the assembly is heated and cooled during manufacture or in operation, the chip and the substrate expand and contract at different rates, so that portions of the chip and substrate move relative to one another. Also, the chip and the substrate can warp as they are heated and cooled, causing further movement of the chip relative to the substrate. These and other effects cause repeated strain on electrical elements connecting the chip and the substrate. The interconnection system should withstand repeated thermal cycling without breakage of the electrical connections. The interconnection system should provide a compact assembly, and should be suitable for use with components having closely-spaced contacts. Moreover, the interconnection should be economical.
Various solutions have been proposed to meet these needs. In particular, as disclosed in U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390 and in International Publication WO 96/02068, flexible leads may be provided between the contacts on a chip or other microelectronic element and the contact pads of a substrate. According to preferred embodiments taught in these documents, a compliant layer, such as an elastomer or a gel may be provided between the chip and the substrate. Flexible leads connecting the chip and substrate may extend through the compliant layer. In these preferred arrangements, the chip is mechanically decoupled from the substrate, so that the chip and substrate can expand and move independently of one another without excessive stress on the electrical connections between the chip contacts and the contact pads of the substrate. Moreover, the assemblies disclosed in these patents and publications meet the other requirements discussed above. In certain preferred embodiments according to these documents, the chip and the interconnections to the substrate can occupy an area of the substrate about the same size as the chip itself.
Microelectronic elements such as semiconductor chips generate considerable amounts of heat during use. For example, a complex, high-speed chip only a few centimeters square in area may produce tens of watts of heat. This heat must be dissipated to maintain the chip at a safe operating temperature. Improvements in chip mountings and electrical connections, and in related assembly methods, have made it possible to reduce the distance between chips so as to achieve a more compact assembly. Such assemblies, typically referred to as xe2x80x9cmultichip modules,xe2x80x9d incorporate one or more substrates with chips disposed close to one another on the substrate. The heat dissipation problems discussed above are particularly extreme in such compact multichip modules.
Considerable effort has been devoted in the art towards meeting these needs for cooling. A general outline of the approaches taken heretofore is set forth in the text Multichip Module Technologies and Alternativesxe2x80x94The Basics, Doane, D. A. and Franzon, P. D., EDS 1993 Van Nostrand Reinhold, New York, N.Y. at chapter 12, pp. 569-613, entitled xe2x80x9cThermal Design Considerations For Multichip Module Applicationsxe2x80x9d (Azar, K., chapter author) and at pages 109-111 of the same reference. As described therein, heat transfer problems in electronic packaging can be addressed in terms of xe2x80x9cthermal resistancexe2x80x9d of the elements involved. The thermal resistance of any element in the heat transfer path refers to the ratio between the temperature difference across such element and the rate of heat flow through the element. Thermal insulators have high thermal resistance whereas elements which convey heat effectively by conduction or convection have low thermal resistance. The overall thermal resistance of the package is the sum of the individual thermal resistances in series in the heat path between the chip and the ambient environment. The overall thermal resistance in turn provides a ratio between the temperature rise of the chips above ambient temperature and the amount of heat produced in the chips.
As described in the aforementioned reference, the heat conduction pathway may include an element commonly referred to as a xe2x80x9cheat sink.xe2x80x9d There is normally a low thermal resistance connection from the heat sink to the environment. For example, the vanes of the heat sink may be bathed in a flow of forced air or liquid. However, there is generally an appreciable thermal resistance between the semiconductor chip, or other microelectronic components, and the heat sink. Stated another way, it is difficult to provide a low thermal resistance connection between the chip and the heat sink while still meeting all of the other requirements for such a connection. This is because the thermal connection must accommodate relative movement between the chips or other components and the heat sink during use of the device. Such relative movement arises in part from movement of the components and the substrate bearing the components as the assembly undergoes temperature changes during use. When the unit is first supplied with power, the temperature of the chips or other components rises faster than the temperature of the substrate, causing differential thermal expansion, warpage and distortion. Further, the coefficients of thermal expansion of the chips and the substrate normally are not matched with the coefficient of thermal expansion of the heat sink, causing further differential thermal expansion and contraction.
Moreover, the connection between the components and the heat sink should accommodate dimensional tolerances in the components, the substrate and the heat sink itself. For example, the chips themselves may be of different thicknesses. Also, the chips can be supported at different levels above the face of the substrate by solder balls or other mountings. The surfaces of the chips may be tilted from their nominal positions, so that the chip surfaces are out of alignment with the surface of the heat sink. The heat sink itself may not be perfectly flat or parallel to the nominal plane of the chip surfaces. Any elements used to connect the heat sink with the chip or the components should be capable of accommodating these tolerances and misalignments. Considerable efforts have been made in the art heretofore towards satisfying these requirements.
Nonetheless, still further improvement would be desirable. For example, it would be desirable to provide additional connection components and methods which provide effective mechanical decoupling and high resistance to thermally induced stresses, while also providing low cost and high reliability. It would also be desirable to provide a microelectronic package including improved assemblies and methods for dissipating heat therefrom to minimize thermally induced stresses, while also providing high reliability and low cost.
One aspect of the present invention provides a method of making a microelectronic assembly including the steps of providing a first microelectronic element, such as a semiconductor chip and a second microelectronic element with confronting spaced-apart surfaces defining a space therebetween and providing one or more masses of a fusible conductive material having a melting temperature below about 150xc2x0 C. in the space. Next, a flowable liquid material, typically a liquid, is introduced between the confronting surfaces of the first and second microelectronic elements and around the one or more fusible conductive masses. The flowable material is then cured to form a compliant layer disposed between the confronting surfaces of the first and second microelectronic elements and surrounding each of the fusible conductive masses. The one or more conductive masses may be maintained in a substantially solid condition or in a substantially liquid condition when the flowable material is introduced. The fusible conductive masses may also be maintained in either a substantially solid condition or in a substantially liquid condition during the curing step.
The first microelectronic element preferably is a circuit element such as a semiconductor chip. The second microelectronic element may be a further circuit element such as a dielectric element having conductors thereon, or else may be a package element such as a casing, heat spreader or heat sink. The conductive material is thermally conductive, electrically conductive or both. Where the second microelectronic element is a circuit element, the method desirably includes the step of electrically connecting the first and second elements to one another. For example, the step of providing the masses of fusible conductive material may be performed so that the masses extend between contacts on the confronting surfaces of the first and second microelectronic element, so that the masses electrically interconnect the first and second elements. The conductive masses desirably provide a thermal conduction path between the first and second microelectronic elements. Preferably, the one or more fusible conductive masses are contiguous with both elements, and connect the first and second microelectronic elements to one another.
Preferably, the fusible conductive masses are contiguous with and are contained by the compliant material, so that the conductive material remains in place when in a liquid state. Thus, the compliant layer keeps the fusible conductive masses separate and electrically insulated from one another. Alternatively or additionally, a polymer coating such as a polyparaxylene coating may be provided over the fusible conductive masses. The polyparaxylene coating is a conformal coating which preferably fully encompasses the fusible conductive masses and desirably extends to the neighboring portions of the confronting surfaces of the first and second microelectronic elements. The coating enhances the electrical isolation of the fusible conductive masses and also protects the masses from contamination, e.g. prevents the fusible conductive material and the compliant layer from diffusing into one another. The polyparaxylene coating can also aid in maintaining the masses in place when the masses are in the liquid state.
In additional preferred methods according to this aspect of the invention, the step of providing said first and second elements being performed so that said second microelectronic element confronts a front surface of the first microelectronic element and these elements define a front space therebetween, the conductive masses being provided in said front space. A third microelectronic element is provided so that this element confront a rear surface. Thus, the first and third microelectronic elements define a rear space between said rear surface and said third microelectronic element. The first microelectronic element is sandwiched between the second and third microelectronic elements, with front and rear spaces on opposite sides of the first microelectronic element. Methods according to this aspect of the invention desirably include the step of disposing one or more additional fusible conductive masses in the rear space and introducing additional flowable material into said rear space and around said conductive masses in said rear space. Most preferably, this additional flowable material is cured to form a rear compliant layer between the third microelectronic element and said first microelectronic element, said rear compliant layer intimately surrounding said conductive masses in said rear space. The step of introducing a flowable material into the rear space, and the step of introducing a flowable material into the front space can be preformed by simultaneously using a single flowable material.
A related aspect of the invention provides a microelectronic package comprising a first microelectronic element such as a semiconductor chip operable in a range of operating temperatures. The chip or other microelectronic element has a front face including contacts and a rear surface. A compliant layer is disposed between the confronting surfaces of the first microelectronic element and the package element. Masses of a fusible, thermally conductive material having a melting temperature within or below the range of operating temperatures of the first microelectronic element are also provided between the package element and the first microelectronic element. Each such mass extends adjacent to the confronting surfaces of the first microelectronic element and the package element for transferring heat therebetween during operation of the microelectronic package. The package may also include a second microelectronic element such as a circuit element electrically connected to the first microelectronic element, most preferably a flexible dielectric sheet with terminals thereon, overlying the front face of the first microelectronic element or chip. A compliant layer most preferably is provided between the front face and the second microelectronic element. Here again, masses of a fusible conductive material, preferably a material capable of conducting both electrical signals and heat, are dispersed in the second compliant layer so that the fusible conductive masses are spaced apart from one another in lateral directions parallel to the surfaces of the microelectronic elements. These masses may be disposed between the opposing contacts on the first microelectronic element and the second microelectronic element for electrically interconnecting the first and second microelectronic elements. In the final package the first and second compliant layers are preferably contiguous with one another. The package mechanically isolates the first microelectronic element or chip and effectively decouples it from mechanical stresses and differential thermal expansion, while also providing effective heat transfer from the chip and effective interconnection between the chip and external circuitry.
The masses of the fusible conductive material used in various aspects of the invention may comprise one or more metals or may comprise a metal alloy and are preferably capable of conducting electrical signals, heat or both. The fusible conductive material preferably has a melting temperature below about 125xc2x0 C., and in more preferred embodiments the fusible conductive material has a melting temperature below about 65xc2x0 C. Most preferably the fusible conductive material has a melting temperature between about 25xc2x0 C. and about 65xc2x0 C. However, lower melting temperatures can be employed if the production process is altered to accommodate the lower melting temperature. The conductive masses preferably are liquid at temperatures within the range of temperatures encountered during normal operation of microelectronic elements, and may have a melting temperature below the range of operating temperatures of the microelectronic elements. The fusible conductive masses may be in a solid state or a liquid state when the assembly is inactive; however, during operation, the fusible conductive masses may be wholly or partially liquid so that essentially no forces will be transmitted between the microelectronic elements through the conductive masses. Stated another way, the conductive masses in their liquid state have spring constants at or close to zero and do not resist movement of the microelectronic elements relative to one another. Alternatively, the conductive material may be a fusible material which melts at temperatures slightly above the range of temperatures encountered during normal operation. In this case, the assembly relieves mechanical stress in the electrical connections or thermal connections, and repairs defects in the connections, when the assembly is exposed to high temperatures during abnormal operating conditions or during processing operations.
Preferably, the compliant dielectric layer also allows the microelectronic elements to move relative to one another. Thus, the dielectric layer desirably is formed from an elastomer, gel, foam or other material having relatively low resistance to deformation. Preferred assemblies according to the present invention thus allow electrical signals to pass between microelectronic elements through the fusible conductive masses. In addition, preferred assemblies according to the present invention also allow heat generated by the microelectronic elements to be effectively dissipated through the package and allow the confronting faces of the microelectronic elements to move relative to one another to compensate for movement and distortion during thermal cycling of the package. The compliant connection between the microelectronic elements also helps to compensate for tolerances encountered during manufacturing and can be provided even where each conductor has substantial cross-sectional area. Thus, low resistance, low impedance conductors can be utilized without impairing the flexible connection. Moreover, when the fusible material melts, cracks or other defects in the conductive masses are repaired.
One or more of the microelectronic elements may include a flexible dielectric sheet having an exterior surface facing away from the other elements and having conductive terminals accessible at the exterior surface. Thus, where the first microelectronic element includes a semiconductor chip, the second element may include a flexible dielectric sheet overlying a surface of the chip and having terminals facing away from the surface of the chip. Thus, the front space lies between the flexible sheet and the chip contact bearing face of the chip. The method may further include the step of forcing the terminals into substantially coplanar disposition while maintaining the masses of fusible conductive material in an at least partially molten condition. Preferably, this step is performed prior to curing the flowable material, either before or after introduction of the flowable material into the space. After the conductive masses have been provided between the confronting surfaces of the chip and the dielectric sheet, the conductive terminals are forced into substantially coplanar alignment with one another as the flowable material is introduced therebetween and the conductive masses are allowed to freeze. Alternatively, the flowable material is introduced between the confronting surfaces before the conductive terminals are forced into substantially coplanar alignment. In certain preferred methods according to this aspect of the invention, the flexible sheet and the chip or other element have contacts on their opposing surfaces. Fusible conductive masses are provided between the opposing contacts to electrically interconnect the chip and the dielectric sheet. Additional fusible conductive masses, aside from those used for electrical interconnection, may be provided between the confronting faces of the chip and the dielectric sheet to provide additional conduct heat therebetween. In an alternative embodiment, the dielectric sheet includes conductive terminals accessible at the exterior surface and flexible leads are used to connect the conductive terminals of the dielectric sheet with the contacts of the semiconductor chip. Fusible conductive masses are provided between the confronting faces of the chip and the dielectric sheet for conducting heat therebetween during operation.
In methods according to further aspects of the invention, one or more of the microelectronic elements may include a plurality of semiconductor chips. For example, the first microelectronic element may include a unitary wafer incorporating a plurality of semiconductor chips, whereas the second microelectronic element may include a flexible dielectric sheet as described above. Each chip is preferably aligned with a portion of the sheet and the contacts on each chip may be connected by the fusible conductive masses to the terminals in the aligned portion of the sheet. The method according to this aspect of the invention may include the further step of severing individual portions of the sheet and wafer to form individual units, each including one or more chips and the portion of the sheet aligned therewith. The step of providing the microelectronic elements and the fusible conductive masses may include the step of providing the masses attached to contacts on one of the microelectronic elements and then juxtaposing the elements with one another and at least partially melting the masses to thereby bond the masses to the contacts on the other element. For example, where one of the elements is a wafer, the masses may be provided on the wafer, and the wafer may be juxtaposed with the flexible dielectric sheet. In methods according to a further aspect of the invention, the second microelectronic element has electrically conductive traces thereon, and a plurality of chips are electrically connected to the second element, as by connection through conductive masses as discussed above, so that the chips are interconnected to one another to form a multichip module.
Further methods of making a microelectronic assemblies according to the invention include the steps of providing a metallic plate, juxtaposing the plate with a surface of a microelectronic element and providing one or more masses of a fusible conductive material so that the masses extend in a space between the plate and the microelectronic element, and preferably extend all the way from the plate to the microelectronic element. In a particularly preferred arrangement, the plate is provided with the more masses of a fusible conductive material disposed at predetermined locations on a surface thereof before juxtaposing the plate with the microelectronic element. Methods according to this aspect of the invention desirably include the step of injecting a flowable material between the metallic plate and the microelectronic element and curing the flowable material to form a compliant dielectric layer which intimately surrounds the fusible conductive masses. The predictable, isotropic thermal expansion properties of the metallic plate help to provide precise alignment of the fusible conductive masses with the contacts on the microelectronic element. The metallic plate is then subdivided to form separate portions connected to separate ones of the fusible conductive masses. The microelectronic element according to this particular embodiment may include an array of semiconductor chips or a semiconductor wafer. The metallic plate may be subdivided by etching the plate after the flowable material is cured. After the metallic sheet has been subdivided, the wafer and the compliant layer may be severed to form individual units whereby each unit includes one or more chips. In certain embodiments, the metallic plate with the fusible conductive masses may be provided by forming a layer on a first side of the metallic plate whereby the layer has apertures therein and includes a material, such as a polymer, which is non-wettable by the conductive masses. The first side of the plate is then exposed to the fusible conductive masses while the conductive masses are in a molten condition so that drops of the fusible conductive masses adhere to the metallic plate at the apertures therein. The first side of the plate is preferably exposed to the conductive masses by dipping the metallic plate into a bath of the fusible conductive material. A second side of the metallic plate opposite from the first side thereof may be covered by a protective coating during the exposing step to prevent the second side of the metallic plate from coming into contact with the fusible conductive material.
Barrier layers, such as a layers of polysilicon, may be provided on surfaces of the microelectronic elements which are in contact with the fusible masses, such as on contacts or on surfaces of package elements. The barrier layer prevents the material in the fusible conductive masses from diffusing into the microelectronic element, the opposing contacts and/or the package element. The barrier metal layer also prevents contamination of the fusible material by the microelectronic element and/or the package element.
Yet a further embodiment of the invention provides structures which can be used as components in fabrication of microelectronic assemblies. A structure according to this aspect of the present invention includes a layer of a matrix material having top and bottom surfaces extending in lateral directions. One or more masses of a fusible conductive material are dispersed in the layer so that the individual conductive masses are spaced apart from one another in the lateral directions and are separated from one another by the matrix material. The fusible conductive masses preferably include one or more metals and preferably have a melting temperature below about 125xc2x0 C. and more preferably below about 65xc2x0 C. In certain embodiments, at least some of the fusible conductive masses extend over a major portion of the distance between the top and bottom surfaces of the layer. In still other embodiments, at least some of the fusible conductive masses extend from the top surface to the bottom surface of the layer to provide a continuous conductive path from the top surface to the bottom surface of the layer. The matrix material is selected from the group consisting of (a) compliant materials having a degradation temperature higher than the melting temperature of the fusible conductive masses and (b)flowable, curable precursor materials. This structure may be provided as a prefabricated structure, without microelectronic elements. The prefabricated structure may be used with one or more microelectronic elements to provide a compliant, thermally conductive connection, and may also be used to provide a compliant electrically conductive connection. The structure may also include one or more removable release layers overlying at least one of the surfaces of the layer of matrix material. The release layer protects the structure from contamination during storage and may be removed from the structure shortly before final assembly of the structure with a microelectronic package. The structure may also include an adhesive overlying at least one of the top and/or bottom surfaces of the matrix layer so that the structure may be easily assembled to the surface(s) of one or more microelectronic elements. Alternatively, the matrix material itself may be capable of bonding to a surface of a microelectronic element. Related aspects of the invention provide assembly methods using such components. For example, a layer as aforesaid may be assembled to one or more semiconductor chips, whereby each semiconductor chip has a surface in engagement with a surface of the layer. Thus, the layer may be applied to a surface of a wafer or to an assemblage of individual chips, and the resulting assembly may be severed to provide individual units including one or more chips and a portion of the layer.
Other objects and advantages of the present invention will be pointed out in the following detailed description and accompanying drawings.